1. Field of the Invention
This invention relates generally to the field of computing technology and more particularly concerns optimization of InfiniBand™ architecture.
2. Description of the Related Art
Most external storage box designs use one or more industry standard peripheral component interconnect (PCI) busses internally to connect between the redundant array of inexpensive disks (RAID) processor, disk drive interconnect initiators, and storage area network (SAN) interfaces, even those which are connected to InfiniBand SANs. However, PCI busses are becoming bottlenecks in external storage box designs.
Current external storage controller designs generally use one or more PCI busses to connect SAN interfaces to controller memory and processors and connect the memory and processors to storage interfaces. The bridge and memory configurations vary from design to design, but FIG. 1 shows an example of such a configuration.
FIG. 1 illustrates a conventional external storage architecture 10. The storage architecture includes hosts 12 and 16 connected to an InfiniBand-PCI (IB-PCI) target channel adapter (TCA) 18 through an InfiniBand fabric 14. The InfiniBand-PCI TCA 18 is connected to a bridge 22 which is in turn connected to a RAID processor 20, memory 24 and SATA host adapters (HA) 30 and 32. From an InfiniBand perspective, it requires one queue pair (QP) per host process, with the RAID processor 20 sending and receiving all SCSI RDMA Protocol (SRP) or (direct access file system) DAFS messages and generating remote direct memory access protocol (RDMA) operations to transfer data to and from the hosts. A queue pair is an endpoint of a link between communicating entities where communication is achieved through direct memory-to-memory transfers between applications and devices. Within the external RAID box all data is transferred by PCI DMA operations and control information by PCI DMA and PCI PIO.
There are numerous disadvantages to this approach, which will become more significant over time. The approach requires that all data pass through the memory block, which doubles memory bandwidth requirements and increases latency. At present, the memory pass through approach is the only option and as data throughput in other parts of the system increase, memory pass through blockage will probably become an increased bottleneck. An additional problem is the bandwidth limitations of parallel, shared busses, such as PCI which can be overloaded with data and therefore decrease data transmission throughput and efficiency. Therefore, as time progresses and data throughput needs becomes greater, the prior art data transmission architecture will generally not have enough capabilities to enable optimal data transmission.
To try to improve scalability and performance, a data transmission system like an InfinaBand™ approach may be used. Prior art InfiniBand networks could be used to improve performance and scalability but performance between host and target is typically not optimum. Switched data may be utilized however there are still scalability concerns.
Typical InfiniBand architecture information may be found in a document called “InfiniBand architecture specification” volume 1 release 1.0.a published by InfiniBand Trade AssociationSM dated Jun. 19, 2001. This document is hereby incorporated by reference.
Therefore, there is a need for a router that is capable of enabling InfiniBand communications which uses RDMA read and write operations to remove PCI bottlenecks and enable direct RDMA communication between a device to a host to optimize data transmission between hosts and targets connected over a network.